PLR135 Photolink Fiber Optic Receiver Datasheet - 650nm Red Light - 2.4-5.5V Supply - 16Mbps NRZ - English Technical Documentation

1. Product Overview

The PLR135 is a compact, high-performance fiber optic receiver module designed for converting optical signals into electrical TTL-compatible signals. It is optimized for operation with red light at a peak sensitivity wavelength of 650nm. The device is built on a proprietary CMOS PDIC (Photodetector Integrated Circuit) process, offering a balance of performance and low power consumption, making it suitable for battery-powered applications. Its core function is to enable reliable digital optical data links.

1.1 Core Advantages and Target Market

The PLR135's key advantages stem from its design optimization. It features high photodiode sensitivity specifically for red light, which is commonly used in plastic optical fiber (POF) systems. A built-in threshold control circuit enhances the noise margin, improving signal integrity in varying conditions. Its low power consumption is a critical feature for portable devices or systems where extended battery life is required. The primary target markets for this receiver include digital audio interfaces, such as those for Dolby AC-3 systems, and general-purpose digital optical data-links for industrial control, consumer electronics, and short-range communication systems.

2. Technical Parameter Deep Dive

This section provides a detailed, objective analysis of the PLR135's specifications as defined in its datasheet.

2.1 Absolute Maximum Ratings

These ratings define the stress limits beyond which permanent damage to the device may occur. Operation outside these ranges is not guaranteed.

• Supply Voltage (Vcc): -0.5V to +5.5V. Applying voltage outside this range risks damaging the internal CMOS circuitry.
• Output Voltage (Vout): Must not exceed Vcc + 0.3V. This protects the output driver stage.
• Storage Temperature (Tstg): -40°C to +85°C. The device can be stored within this range without degradation.
• Operating Temperature (Topr): -20°C to +70°C. The device is guaranteed to meet its electrical specifications within this ambient temperature range.
• Soldering Temperature (Tsol): 260°C for a maximum of 10 seconds. This is typical for lead-free reflow soldering processes.
• ESD Ratings: Human Body Model (HBM): 2000V; Machine Model (MM): 100V. These indicate the level of electrostatic discharge the device can withstand, guiding handling and assembly procedures.

2.2 Recommended Operating Conditions

For normal operation and to guarantee the performance listed in the electro-optical characteristics, the device should be operated within these conditions.

• Supply Voltage (Vcc): 2.4V (Min), 3.0V (Typ), 5.5V (Max). A typical operating point is 3.0V or 3.3V.

2.3 Electro-Optical Characteristics

These parameters are measured under specific conditions (Ta=25°C, Vcc=3V, CL=5pF) and define the receiver's performance.

• Peak Sensitivity Wavelength (λp): 650 nm. The receiver is most sensitive to light at this red wavelength.
• Transmission Distance (d): 0.2 to 5 meters. This range is typical for standard plastic optical fiber (POF).
• Optical Power Range (Pc): Minimum Receiver Power (Pc,min): -27 dBm (Min); Maximum Receiver Power (Pc,max): -14 dBm (Max). The input optical power must fall within this -27 dBm to -14 dBm window for proper operation at 16 Mbps. Exceeding the maximum can saturate the receiver.
• Dissipation Current (Icc): 4 mA (Typ), 12 mA (Max). This quiescent current directly impacts system power consumption.
• Output Voltage Levels: High Level Output Voltage (VOH): 2.1V (Min), 2.5V (Typ) with Vcc=3V. Low Level Output Voltage (VOL): 0.2V (Typ), 0.4V (Max). These are standard TTL-compatible levels.
• Dynamic Performance:
  • Rise/Fall Time (tr, tf): 10 ns (Typ), 20 ns (Max).
  • Propagation Delay (tPLH, tPHL): 120 ns (Max).
  • Pulse Width Distortion (Δtw): ±25 ns (Max). The difference between low-to-high and high-to-low delays.
  • Jitter (Δtj): Varies with input power. At -14 dBm: 1 ns (Typ), 15 ns (Max). At -27 dBm: 5 ns (Typ), 20 ns (Max). Jitter increases as the signal approaches the minimum sensitivity.
• Transfer Rate (T): 0.1 to 16 Mbps for NRZ (Non-Return-to-Zero) signals. This defines the data rate capability.

3. Performance Curve Analysis

The datasheet provides typical performance curves that are crucial for design.

3.1 Voltage vs. Sensitivity

Figure 4 shows the relationship between operating voltage and minimum receiver power (sensitivity). Sensitivity generally improves (becomes a more negative dBm number, meaning it can detect weaker signals) as the supply voltage increases from 2.4V towards 5.5V. For example, at 3.3V, the sensitivity might be around -28 dBm for 16 Mbps, whereas at 5.0V it could improve to -29 dBm. This curve is essential for designers choosing an operating voltage for their specific sensitivity requirement.

3.2 Data Rate vs. Sensitivity

Figure 5 illustrates the trade-off between data rate and receiver sensitivity. As the data rate increases, the minimum optical power required for error-free operation also increases (the sensitivity becomes worse, a less negative dBm). At 16 Mbps and 3.3V, the sensitivity might be -28 dBm, but at 25 Mbps, it could degrade to -24 dBm. This graph is critical for determining the maximum possible link length or the required transmitter power for a desired data rate.

4. Mechanical and Package Information

4.1 Package Dimensions and Pinout

The PLR135 comes in a compact 3-pin package. The pin functions are clearly defined:

1. Pin 1: Vout - TTL Output Signal.
2. Pin 2: GND - Ground.
3. Pin 3: Vcc - Supply Voltage (2.4V - 5.5V).

The dimensional drawing specifies the exact physical size, lead spacing, and positioning. General tolerance is ±0.10 mm. Accurate footprint design based on this drawing is necessary for proper PCB assembly.

5. Application Circuits and Design Guidelines

5.1 Standard Application Circuits

The datasheet provides two reference circuits: one for a 3V supply and another for a 5V supply. Both circuits are fundamentally similar, emphasizing proper power supply decoupling.

• A 0.1 µF ceramic capacitor (C1) must be placed as close as possible to the Vcc and GND pins of the PLR135, ideally within 7mm. This capacitor provides a low-impedance path for high-frequency noise on the power rail, which is critical for maintaining low jitter performance.
• An inductor (L2, 47 µH) is placed in series with the power supply line. This helps to isolate the receiver's power node from digital noise originating elsewhere on the board.
• For the output, a small load capacitor (C2, 30 pF suggested) may be used, but its value should be minimized as it affects rise/fall times.

5.2 PCB Layout Recommendations

To achieve the specified jitter and low input power performance, careful PCB layout is mandatory:

1. Decoupling: The 0.1 µF decoupling capacitor must be a surface-mount type (0805 or smaller) and placed within 2 cm of the device's Vcc and Gnd pins. This minimizes parasitic inductance in the decoupling path.
2. Power Planes: Implementing isolated Vcc and GND planes beneath the POF receiver area is highly recommended. The device should be mounted directly over these planes. This creates a planar capacitance that acts as a high-frequency filter, significantly reducing noise coupling from other digital circuits on the motherboard.
3. Signal Isolation: Keep the sensitive input path (the fiber interface area) and the output trace away from noisy digital lines or switching power supplies.

6. Packaging and Ordering Information

6.1 Label Explanation and Packing

The product label contains several codes for traceability and specification:

• P/N: Product Number (e.g., PLR135).
• CPN: Customer's Part Number (if assigned).
• LOT No.: Manufacturing lot number for traceability.
• Other codes like CAT, HUE, and REF are internal ranking codes for various parameters (not detailed in the public datasheet).

The standard packing specification is 250 pieces per bag, with 4 bags per box (total 1000 pieces per box).

7. Application Notes and Design Considerations

7.1 Typical Application Scenarios

• Digital Audio Interfaces: Ideal for consumer audio equipment using Toslink or similar plastic fiber for S/PDIF or Dolby Digital (AC-3) signal transmission, providing galvanic isolation and noise immunity.
• Industrial Data Links: Used in factory automation, control systems, and sensor networks where electrical noise immunity, safety isolation, or data security over short distances is needed.
• Consumer Electronics: Can be found in set-top boxes, gaming consoles, or high-end TVs for internal or external digital audio connections.

7.2 Critical Design Considerations

1. Optical Power Budget: The designer must calculate the total link loss (fiber loss, connector loss) and ensure the optical power at the receiver (Pc) is between the minimum (-27 dBm) and maximum (-14 dBm) limits. The performance curves (Figs. 4 & 5) must be consulted for the chosen voltage and data rate.
2. Jitter Management: Jitter performance is highly dependent on input power and PCB layout. Operating near the minimum sensitivity will increase jitter. Strict adherence to the decoupling and layout guidelines is non-negotiable for high-data-rate or low-power applications.
3. Voltage Selection: While the device operates from 2.4V to 5.5V, the choice affects sensitivity and power consumption. A higher voltage improves sensitivity but may increase power dissipation slightly.

8. Technical Comparison and Differentiation

While a direct side-by-side comparison with other models is not provided in this single datasheet, the PLR135's key differentiators can be inferred:

• Optimized for 650nm Red Light: Many generic receivers have a broader sensitivity range, but optimization for 650nm POF systems can yield better sensitivity at that specific wavelength compared to a broadband device.
• Built-in Threshold Control: This feature automatically adjusts the decision threshold, improving the noise margin over varying conditions (like temperature or aging of the transmitter). Not all basic receivers include this, making the PLR135 more robust.
• CMOS PDIC Process: Integration on a CMOS platform typically allows for lower power consumption and better compatibility with modern digital systems compared to older bipolar or discrete designs.

9. Frequently Asked Questions (FAQ)

Q1: What is the maximum data rate for the PLR135?

A1: The PLR135 supports NRZ data rates from 0.1 Mbps up to 16 Mbps, as specified in the datasheet. Attempting to run it faster may result in increased bit errors.

Q2: Can I use this receiver with infrared (850nm or 1300nm) fiber optic cable?

A2: No. The device is specifically optimized for a peak sensitivity of 650nm (red light). Its sensitivity at infrared wavelengths will be significantly lower, likely making it unusable for standard IR-based fiber systems.

Q3: My input optical power is -30 dBm. Will the PLR135 work?

A3: No. The specified minimum receiver power is -27 dBm. A -30 dBm signal is below the sensitivity threshold, and the receiver will not reliably detect it. You need a more sensitive receiver, a higher-power transmitter, or a lower-loss fiber link.

Q4: How critical is the 0.1 µF decoupling capacitor placement?

A4: Extremely critical. Poor decoupling is the most common cause of excessive jitter and erratic operation in high-speed receiver circuits. Placing it within 2 cm (and ideally much closer) is a firm requirement, not a suggestion.

Q5: What does "NRZ signal" mean?

A5: NRZ stands for Non-Return-to-Zero. It is a common digital encoding scheme where a high signal level (e.g., light ON) represents a logical '1' and a low level (light OFF) represents a logical '0'. The signal does not return to a neutral state between bits.

10. Operating Principle Introduction

The PLR135 operates on a fundamental optoelectronic principle. Light from a 650nm optical fiber is focused onto a photodiode (PD) integrated into the CMOS chip. The photodiode converts the incident photons into a proportional photocurrent. This tiny current is then fed into a high-gain, low-noise transimpedance amplifier (TIA), which converts it into a voltage signal. Following the TIA, a limiting amplifier boosts the signal to a consistent digital level. The built-in threshold control circuit dynamically adjusts the decision point for the digital slicer, compensating for baseline wander and low-frequency noise to improve the bit-error-rate. Finally, an output buffer stage delivers a clean, TTL-compatible digital signal corresponding to the original optical input.

11. Industry Trends and Context

Devices like the PLR135 represent a mature and optimized segment of the fiber optic component market. The trend in such consumer and industrial-grade short-reach optical links is towards:

• Higher Integration: Combining the receiver photodiode, amplifier, and digital logic into a single CMOS die (as seen here) reduces size, cost, and power.
• Lower Power Consumption: Driven by portable and battery-operated devices, newer generations continually push for lower operating currents.
• Increased Data Rates: While 16 Mbps is sufficient for audio and many control applications, the demand for video and faster data transfer pushes development towards receivers capable of 100 Mbps and beyond over POF.
• Improved Robustness: Features like automatic threshold control and higher ESD protection are becoming standard to improve reliability in real-world, noisy environments.

The PLR135 fits into applications where reliability, noise immunity, and galvanic isolation are more critical than extreme data rate or distance, which are the domains of glass fiber and laser-based systems.